Embedded overcurrent protection circuits within power converters completely shut-off the respective power converter which remains off until the overcurrent condition is removed and the input power has recycled. This function is desirable to protect the power converter from internal or external component failure and to prevent excessive heating in those failed components. These circuits have been used in power supplies for more than a decade. Advantages of these circuits include increased functionality and efficiency in cost using a minimum number of components. More specifically, overcurrent protection circuits are very simple.
A conventional buck power converter 100 includes a PWM controller 30 that couples to a driver which couples directly to the control node a power switch as is shown in FIG. 1. Depending upon the applications, the power switch may be a PMOS or a NMOS device. In particular in FIG. 1, the power switch is the PMOS transistor 14. Current limit sense circuits, 18 and 20, connect to sense the drain-to-source voltages Vsd of the PMOS transistor 14. To further improve the power conversion efficiency, it is a common practice to add a synchronous rectifier, such as the NMOS transistor 16, connected in parallel with a Schottky diode 32. As a means of preventing the inductor 34 connected to the drain nodes of each switch from being saturated, it is necessary to monitor and limit the inductor current within the PWM Buck converter 100.
As shown, in integrated circuits where the power switches, 14 and 16, are built-in on the chip, this monitoring is usually done by sensing the voltage drop across the power switch 14 when the switch is turned on. As described, the current limit sense circuits, 18 and 20, connect across each transistor, 14 and 16, to sense the drain-to-source voltage of each transistor, 14 and 16. The output voltage across the capacitor 36 connected to the inductor 34 is feedback through a filter 24 to a main error comparator 22. The main error comparator 22 compares the filtered output voltage with a reference voltage signal, typically a sawtooth wave as shown. The main error comparator 22 provides the result to the PWM controller 10. Effectively, the monitoring circuit including the feedback scale 24 and the main error comparator 22 compares this voltage drop with the preset reference voltage to determine whether the inductor current exceeds the current limit and initiate actions to protect the inductor 34.
With the described current limit scheme, whenever the comparator 22 detects the sensed voltage drop exceeds the reference, i.e. the inductor current is over the preset limit, it triggers the protection circuit to turn off the PMOS power switch 14 for the rest of the clock period. A simplified current limit state diagram 200 for the known buck power converter of FIG. 1 is shown in FIG. 2. Initially, the current limit detection circuit is reset in step 202. The power switch 14 is turned on in step 204. After a determination of whether the PMOS current is over the limit, if the PMOS current is not over the limit, the PWM feedback loop decision is made in step 206. On the rising edge of the system clock, the current limit detection circuit is reset in step 202. If, in the alternative, the PMOS current is over the limit, step 208 dictates that the PMOS power switch 14 is shut off. Afterwards on the rising edge of the system clock, the current limit detection circuit is reset in step 202. Using this scheme in step 202, the current limit detection circuit must be reset at the beginning of every clock cycle. In other words, the PMOS power switch 14 has to be turned on every clock period to sample the current in the form of a voltage drop across the switch before the detection circuit, including elements 18, 20, 22 and 24, can determine whether the output current exceeds its limit. Since the detection circuit has no information about the inductor current level when the switch is open, the current limit detection has to be reset on every clock cycle.
Since current limit detection is reset every clock cycle, however, the PMOS power switch 14 turns on for a short period of time in every clock cycle. The length of time the switch 14 is turned on is determined by how fast the comparator 22 can react to the over current and the feedback loop delay. Although the length of time for the turn-on period is short, the inductor current builds up during this turn-on period until the power switch 14 is turned off. The inductor current begins to decrease once the power switch 14 is turned off, where the slope of the inductor current depends on the output voltage.
Even this short turn-on period of the power switch 14 in every clock cycle presents a substantial problem given certain input and output conditions. For example, when the output of the buck power converter 100 is accidentally shorted to ground and the input voltage is relatively high, the current limit circuit 18 may not be able to limit the inductor current at all. In addition, when the power switch 14 is on, the output current could ramp up swiftly due to the large voltage across the inductor 34. Moreover, when the power switch 14 is off as shown in step 208, the current decreases extremely slow since the reverse voltage across the inductor 34 is relatively small and the addition of the synchronous rectifier, NMOS transistor 16, makes the current decrease further. If the delay arising from resetting the current limit during turn-on time of the power switch 14 which includes time to detect the current limit and to turn off power switch is too long, the output current could build up too quickly. As a result, the current limit system is not able to keep the current within the preset limit. To avoid this problem, the comparator 22 and the steps (202, 204, and 206) required to detect the current limit have to be fast enough to minimize the turn-on period of the PMOS power switch 14. A fast comparator 22, however, is usually undesirable for a low power system since it will require a larger amount of current consumption.
The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems set forth above.